Technical Lead Engineer

ASIC Micro-architect, RTL Design and Implementation Engineer
Participate in the design of complex, high-performance, and highly
integrated Network Processor used in several of Cisco routing platforms

Responsibilities include:
Architecture definition/analysis and feasibility studies.
Detailed micro-architecture specification, RTL logic design, synthesis
and timing closure.
Will work closely with verification team members to develop test plans and actively participate in logical design debug.
May participate in synthesis, floorplanning, place and route, timing analysis, power consumption, signal integrity and power integrity.

Skills Required:
Experience in high-performance ASIC design.
Good understanding of ASIC methodologies and flows.
Hands-on experience with HDL languages and tools, scripting and
programming languages (Perl, TCL).
Can make design tradeoffs between logical and physical design to optimize for
logical requirements, physical complexity, speed, area, power and schedule.
Desired to have prior experience in clock and power distribution and analysis, RC extraction and correlation, place and route and tapeout issues.
Knowledge of deep sub-micron issues as they relate to routing, power and timing.